1. Field of the Invention
The present invention generally relates to a shift register and a programmable logic circuit, and more particularly, to a chain-connected shift register and a programmable logic circuit using the chain-connected shift register which may be constructed with an extremely small size.
The present invention is further directed to a programmable logic circuit and a programmable-logic-circuit system constructed with a plurality of programmable logic circuits, whose logic functions are changeable during a circuit operation. Therefore, a number of realizable logic circuits in the programmable logic circuit may be significantly increased.
2. Description of the Related Art
For a programmable logic circuit, for example, a field programmable gate array (FPGA) is commonly well known. FIG. 1 shows a block diagram of a typical configuration example of the field programmable gate array (FPGA). The FPGA has a plurality of logic cells, each of which may program a desired logic circuit, and a plurality of wires which can flexibly connect the plurality of logic cells to each other. By providing configuration data describing a configuration of the logic circuit into each logic cell, a large number of logic circuits may be flexibly provided. For methods of storing the configuration data, at present, the following three types of FPGA are used.
I. SRAM-program-type FPGA
The configuration data is stored in a SRAM memory cell. Functions of the logic circuit may be repeatedly changed. When manufacturing the FPGA, there is no need for a specific process technique.
II. Nonvolatile-memory-program-type FPGA
The configuration data is stored in a nonvolatile memory such as an EEPROM or a flash memory. In the same way as the SRAM-program-type FPGA, functions of the logic circuit may be repeatedly changed. However, when manufacturing the FPGA, there is a need for a specific process technique.
III. Antifuse-program-type FPGA
According to the configuration data, conditions of switches (anti fuses) provided on an LSI chip are permanently determined. After programing is finished, functions of the logic circuit may not be changed. When manufacturing the FPGA, there is a need for a specific process technique.
Further, by flexibly connecting and combining a plurality of programmable logic circuits, a still further large number of logic circuits may be constructed, which are referred to as a programmable-logic-circuit system.
In addition, recently, in order to carry out a logic operation test of the large number of logic circuits on a circuit board which is in practical use, a hardware emulator is developed. In the hardware emulator, a plurality of FPGAs are connected to each other in a programed condition, and the large number of logic circuits are constructed. As compared to a software simulator operable in a work station, the hardware emulator is operable at a high speed more than 100 times the operation speed of the software simulator. Therefore, the hardware emulator may be widely used for developing a microprocessor, etc.
In the SRAM-program-type FPGA, the configuration data is commonly serially loaded into a configuration memory. Therefore, in general, the configuration memory is constructed with a shift register.
Further, the shift register may be commonly constructed by connecting a plurality of D-type flip-flops in series. FIG. 2 shows a schematic diagram of a typical CMOS-D-type flip-flop. In the D-type flip-flop, by connecting an inverter INV and a transmission gate TG in a ring formation, a closed loop is formed. An input signal provided to an input terminal IN is transmitted to an output terminal OUT through a master-slave latch constructed with two closed loops. The D-type flip-flop shown in FIG. 2 has 16 MOS transistors. Therefore, a prior-art shift register constructed with such D-type flip-flops requires a relatively large area on an LSI chip.
Particularly, since the SRAM-program-type FPGA requires hundreds of thousands of stages of shift registers in order to store the configuration data, an extremely large area of the FPGA chip is used for the configuration memory constructed with the shift registers. In general, performance of the FPGA is evaluated by an equivalent gate number per unit area (evaluation index indicating a number of gates corresponding to realizable maximum logic circuits). Therefore, to improve performance of the FPGA, there is a need for miniaturizing a size of the configuration memory constructed with the shift register, and for reducing a ratio of a memory area to an overall chip area.
For miniaturizing the shift register, it is well known that it is advantageous to use a chain-latch-structure shift register. FIG. 3 shows a schematic diagram of a prior-art chain-latch-structure shift register. FIG. 4 shows an illustration for explaining an operation of the prior-art chain-latch-structure shift register shown in FIG. 3.
In FIG. 4, a signal provided to a terminal K, when a switch C is turned on and switches E, F are turned off, passes an inverter D and transmits to an output terminal of the inverter D. After that, when the switch C is turned off and the switches E, F are turned on, a value of the provided signal is held in a closed loop A. After the value in the closed loop A stabilizes and is fixed, the switch C is turned on and the switches E, F are turned off again, and also, switches H and I are turned on. At this time, until an output value of an inverter G changes, it is necessary to operate a switch H and fix an output of an inverter J. If the switch I is turned before the output of the inverter J is fixed, a value to be held in a closed loop B may be lost by a value which has been held in a closed loop Axe2x80x2.
There is the following disadvantage in the above-discussed prior-art chain-latch-structure shift register.
When the above-discussed chain-latch-structure shift register is practically constructed, dispersion in operation performance may occur due to performance of the switches constructing the shift register, wire-load capacitance, timing of a supplied clock, etc. Therefore, it is difficult to obtain a stable operation in that shift register.
Further, in the prior-art programmable logic circuit, there is the following disadvantage.
In general, for methods of constituting the flip-flop using the logic cell in the programmable logic circuit, the following two methods are known:
I. Individual Flip-flop Type
In the logic cell, the flip-flop is individually provided in addition to a programmable function unit. Input and output of the flip-flop are controlled by the configuration data.
II. Program Feedback Type
In the programmable function unit provided in the logic cell, a feedback path is provided. When a connecting instruction is produced from the configuration data, the flip-flop is established.
In both the types, a number of the realizable flip-flops in the programmable logic circuit is determined by a number of the logic cells. Therefore, to increase the number of the realizable flip-flops, it is required to increase the number of the logic cells. However, this requirement causes the chip area of the programmable logic circuit to increase.
In addition, in the prior-art programmable logic circuit and the prior-art programmable-logic-circuit system, before the circuit operation is started, the configuration data is loaded into the configuration memory to determine logic functions of the programmable function unit. After the configuration data is loaded, the programmable logic circuit is operative according to the logic functions determined by the configuration data until all configuration data-in the programmable logic circuit is changed.
Namely, the logic functions programmed in the programmable logic circuit are fixed until the operation according to the logic functions is finished. Therefore, to increase the-realizable logic functions (or corresponding gate number) in the programmable logic circuit and the programmable-logic-circuit system, it is required to enlarge a size of the logic cell and to increase the number of logic cells. In this case, these requirements also cause the chip area of the programmable logic circuit to increase.
It is an object of the present invention to provide a small-sized shift register. Using the shift register, a circuit constructed with a large number of shift registers, for example, a configuration memory in a programmable logic circuit, may be miniaturized.
It is another object of the present invention to provide a programmable logic circuit in which a number of realizable flip-flops may be increased.
It is still another object of the present invention to provide a programmable logic circuit and a programmable-logic-circuit system. In the circuit and system, configuration data in the configuration memory may be changed during operation of the circuit and system. Also, a portion of the programmable logic circuit may be flexibly initialized. Therefore, a number of realizable logic circuits (corresponding to a substantially realizable gate number) in the programmable logic circuit and the programmable-logic-circuit system can be increased. As a result, cost of the programmable logic circuit and the programmable-logic-circuit system may be extremely reduced.
This permits the disadvantages described above to be eliminated.
The object described above is achieved by a shift register having a plurality of circuit cells successively connected in a chain formation, each of the circuit cells comprising: a first inversion gate; a first transmission gate, connected to an output of the first inversion gate, being switched by a clock; a second inversion gate connected to an output of the first transmission gate; a first P-channel transistor, connected between an output of the second inversion gate and an input of the first inversion gate, being switched by the clock; a second transmission gate, connected to the output of the second inversion gate, being switched by an inversion clock; and a second P-channel transistor, connected to the output of the first transmission gate, being switched by the inversion clock; wherein the plurality of circuit cells are successively connected such that the input of the first inversion gate of the circuit cell is connected to an output of a second transmission gate of a former-stage circuit cell, and the output of the first inversion gate of the circuit cell is connected to an output of a second P-channel transistor of the former-stage circuit cell.
According to the above-discussed shift register, a transmission time for passing through a main signal path is less than that for passing through a feedback circuit. Therefore, operation timing in the chain-latch-structure shift register may be stabilized.
By using the above-discussed chain-latch-structure shift register, a number of gates and a chip area for constituting the shift register may be reduced to less than half of those of a prior-art shift register. Further, in a programmable logic circuit using a large number of shift registers for a memory, a chip area for the memory may be reduced, and a number of realizable logic circuits for the chip area may be increased.
The object described above is also achieved by the shift register mentioned above, further comprising a clock supplying circuit for supplying the clock and the inversion clock, the clock supplying circuit having a first buffer circuit buffering an input clock and producing the clock and a second buffer circuit inverting the input clock and producing the inversion clock, wherein as least one of the first buffer circuit and the second buffer circuit has an inverter whose transistor parameter is adjusted so that a driving ability on a P-channel transistor side is substantially equal to or larger than that on an N-channel transistor side.
The object described above is also achieved by the shift register mentioned above, further comprising a clock supplying circuit for supplying the clock and the inversion clock, the clock supplying circuit having a first buffer circuit buffering an input clock to produce the clock and a second buffer circuit inverting the input clock to produce the inversion clock, wherein as least one of the first buffer circuit and the second buffer circuit has an inverter in which a number of P-channel transistors is substantially larger than that of N-channel transistors.
According to the above-discussed shift register, the driving ability on the P-channel transistor side is substantially larger than that on the N-channel transistor side. Therefore, in the clock output of the clock supplying circuit, a rising time of the clock edge may be substantially the same as a falling time thereof. By the above-discussed conditions, a stable operation of the chain-latch-structure shift register may be positively carried out.
The object described above is also achieved by the shift register mentioned above, further comprising a state setting circuit, connected to one input terminal of a first NAND gate and one input terminal of a second NAND gate, for setting a state in the circuit cell.
The object described above is also achieved by the shift register mentioned above, further comprising a state setting circuit, connected to one input terminal of a first NOR gate and one input terminal of a second NOR gate, for setting a state in the circuit cell.
According to the above-discussed shift register, by the state setting circuit, the internal state in the chain-latch-structure shift register may be flexibly set.
The object described above is also achieved by the shift register mentioned above, wherein each of the circuit cells further comprises a data output terminal, and the shift register further comprises a decoder circuit, connected to the data output terminals of the circuit cells, producing one data set from the data output terminals according to a control input signal.
According to the above-discussed shift register, by providing the control signal to the decoder circuit, an output according to the logic function determined by the memory data is obtained. Namely, with the decoder circuit and the shift register, a desired logic circuit may be constructed.
The object described above is also achieved by the shift register mentioned above, further comprising a clock control circuit connected to clock input terminals of the first and second transmission gates and the first and second P-channel transistors of selected ones of the circuit cells, the clock control circuit supplying the clock and the inversion clock to the clock input terminals in a-first mode, and supplying a given signal to selected ones of the clock input terminals so as to isolate the part of the circuit cells from the remaining circuit cells and supplying a signal to the remaining clock input terminals in a second mode, wherein in the second mode, the selected ones of the circuit cells are operable as a flip-flop.
The object described above is also achieved by a programmable logic circuit having a configuration memory being providing with configuration data, and at least one logic cell operating with a desired logic function according to the configuration data, the configuration memory including a shift register which has a plurality of circuit cells successively connected in a chain formation, each of the circuit cells comprising: a first inversion gate; a first transmission gate, connected to an output of the first inversion gate, being switched by a clock; a second inversion gate connected to an output of the first transmission gate; a first P-channel transistor, connected between an output of the second inversion gate and an input of the first inversion gate, being switched by the clock; a second transmission gate, connected to the output of the second inversion gate, being switched by an inversion clock; and a second P-channel transistor, connected to the output of the first transmission gate, being switched by the inversion clock; wherein the plurality of circuit cells are successively connected such that the input of the first inversion gate of the circuit cell is connected to an output of a second transmission gate of a former-stage circuit cell, and the output of the first inversion gate of the circuit cell is connected to an output of a second P-channel transistor of the former-stage circuit cell.
According to the above-discussed shift register and the programmable logic circuit, by the given signal to selected ones of the circuit cells in the chain-latch-structure shift register, the selected ones of the circuit cells are operable as a flip-flop. Therefore, when the above-discussed shift register is applied to the configuration memory of the programmable logic circuit, a part of the configuration memory may be used for a flip-flop. As a result, a number of realizable flip-flops in the logic cell may be increased.
The object described above is also achieved by the programmable logic circuit mentioned above, wherein each of the first and second inversion gates has one of a NAND gate and a NOR gate, and a state of the circuit cell is set by supplying a given signal from one of the NAND gate and the NOR gate to the circuit cell.
According to the above-discussed programmable logic circuit, the state of the circuit cell in the logic cell may be flexibly set.
The object described above is also achieved by a programmable logic circuit programming a desired circuit function according to configuration data, the programmable logic circuit comprising a plurality of partial circuits, wherein during operation of the programmable logic circuit, when a control signal is applied to at least one partial circuit in the programmable logic circuit, a circuit function previously realized in the at least one partial circuit is changed to another circuit function without influencing an operation of other partial circuits in an operating condition.
The object described above is also achieved by a programmable-logic-circuit system programming a desired circuit function according to configuration data, the programmable-logic-circuit system comprising a plurality of second partial circuits which respectively include programmable logic circuits, wherein during operation of the programmable-logic-circuit system, when a control signal is applied to at least one second partial circuit in the programmable-logic-circuit system, a circuit function previously realized in the at least one second partial circuit is changed to another circuit function without influencing an operation of other second partial circuits in an operating condition.
According to the above-discussed programmable logic circuit and programmable-logic-circuit system, when the programmable logic circuit or the programmable-logic-circuit system is in an operating condition, the circuit function programed in at least one partial circuit may be changed without influencing the operation of other partial circuits in the operating condition. By changing of the circuit function, the logic function, the connection function, and the data input-and-output function may be changed. Accordingly, a number of programmable circuits may be increased larger than that physically determined by a number of gates.
The object described above is also achieved by the programmable logic circuit mentioned above, further comprising at least one configuration-data server providing configuration data to at least one of the partial circuits through one of a dedicated wire line and a programmable wire line.
The object described above is also achieved by the programmable-logic-circuit system mentioned above, further comprising at least one configuration-data server providing configuration data to at least one of the second partial circuits through one of a dedicated wire line and a programmable wire line.
According to the above-discussed programmable logic circuit and programmable-logic-circuit system, the configuration-data server for supplying the configuration data is included, and the configuration data is provided to the partial circuits through the dedicated wire line or the programmable wire line. Therefore, the configuration data may be efficiently provided to the partial circuits, and, thus, circuit configurations of the programmable logic circuit and the programmable-logic-circuit system may be simplified.
The object described above is also achieved by the programmable logic circuit mentioned above, wherein at least one of the partial circuits comprises a storage device storing a plurality of configuration data, wherein when the plurality of configuration data are switched by an external control signal, a previously programed circuit function in the partial circuit is instantaneously changed to another circuit function.
The object described above is also achieved by the programmable-logic-circuit system mentioned above, wherein at least one of the second partial circuits comprises a storage device storing a plurality of configuration data, wherein when the plurality of configuration data are switched by an external control signal, a previously programed circuit function in the second partial circuit is instantaneously changed to another circuit function.
According to the above-discussed programmable logic circuit and programmable-logic-circuit system, the partial circuit includes the storage circuit storing a plurality of configuration data. Therefore, by switching the configuration data, the circuit function realized in the partial circuit may be instantaneously changed.
The object described above is also achieved by the programmable logic circuit mentioned above, further comprising an interface connecting to the programmable logic circuit at least one external configuration-data server which provides configuration data to at least one of the plurality of partial circuits.
The object described above is also achieved by the programmable-logic-circuit system mentioned above, further comprising an interface connecting to the programmable-logic-circuit system at least one external configuration-data server which provides configuration data to at least one of the plurality of second partial circuits.
According to the above-discussed programmable logic circuit and programmable-logic-circuit system, the interface for connecting the configuration-data server is provided. Therefore, since the configuration-data server may be provided outside of the programmable logic circuit and the programmable-logic-circuit system, the programmable logic circuit and the programmable-logic-circuit system may be simplified. Further, for the configuration-data server, a large size and high performance device such as a personal computer is usable.
The object described above is also achieved by the programmable logic circuit mentioned above, further comprising a control device selecting a given partial circuit from the plurality of partial circuits through one of a dedicated wire line and a programmable wire line, and selectively changing a circuit function of the given partial circuit to another circuit function.
The object described above is also achieved by the programmable-logic-circuit system mentioned above, further comprising a control device selecting a given second partial circuit from the plurality of second partial circuits through one of a dedicated wire line and a programmable wire line, and selectively changing a circuit function of the given second partial circuit to another circuit function.
According to the above-discussed programmable logic circuit and programmable-logic-circuit system, the control device selectively changing the circuit function of the given partial circuit is provided. The control device is connected to the partial circuit through the dedicated wire line or the programmable wire line. Therefore, when the programmable logic circuit is in an operating condition, only the circuit function of the given partial circuit may be efficiently changed.
The object described above is also achieved by the programmable logic circuit mentioned above, further comprising an interface connecting to the programmable logic circuit an external control device which selects a given partial circuit from the plurality of partial circuits and selectively changes a circuit function of the given partial circuit to another circuit function.
The object described above is also achieved by the programmable-logic-circuit system mentioned above, further comprising an interface connecting to the programmable-logic-circuit system an external control device which selects a given second partial circuit from the plurality of second partial circuits and selectively changes a circuit function of the given second partial circuit to another circuit function.
According to the above-discussed programmable logic circuit and programmable-logic-circuit system, the interface for connecting the control device is provided. Therefore, since the control device may be provided outside of the programmable logic circuit and the programmable-logic-circuit system, the programmable logic circuit and the programmable-logic-circuit system may be simplified. Further, for the control device, a large size and high performance device such as a personal computer is usable.
The object described above is also achieved by the programmable logic circuit mentioned above, wherein the logic cell comprises an output-data holding circuit for holding output data of the logic cell, wherein when the programmable logic circuit is operating and when a programed circuit function in the logic cell-is being changed, the output data of the circuit cell is held by the output-data holding circuit so as to prevent from influencing other partial circuits in an operating condition.
According to the above-discussed programmable logic circuit, when the circuit function realized in the logic cell is changed, the output of the logic cell is held by the output-data holding circuit. Therefore, even when the circuit function of the given logic cell is changed, it is prevented from influencing the operation of other logic cells in an operating condition.
The object described above is also achieved by the programmable logic circuit mentioned above, wherein the shift register comprises a chain-latch-structure shift register.
According to the above-discussed programmable logic circuit, the shift register in the configuration memory is constructed with the chain-latch-structure shift register. Therefore, the programmable logic circuit may be miniaturized.
The object described above is also achieved by the programmable logic circuit mentioned above, wherein the second configuration data supplied to the memory controller is generated based on an output signal from another logic cell.
According to the above-discussed programmable logic circuit, the configuration data supplied to the memory controller is generated based on the output signal produced from another logic cell. Therefore, since it is unnecessary to externally supply the configuration data, by a self-control operation, a number of programmable circuits in the programmable logic circuit may be increased larger than the number of programmable circuits physically determined by the number of gates.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.